invert_pwm_1cog_6pin

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By: created: 2014-08-05 | updated: 2014-08-05

A single cog 3-phase inverter PWM object capable of programmable dead-time and driving 6 pins.

The limitation is that the frequency is fixed w.r.t. master clock.  The granularity is 4 clock cycles as instructions are used to drive the pins rather than waitcnt.

The operating frequeency is Mclk / 3440 and the samples are read and used at twice this rate, Mclk / 1720, so that each edge of the symmetric, phase-correct, PWM signals is controlled.

The pins can be any 6 pins.

Example provided

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Package icon invert_pwm_1cog_6pin_test-bst-archive-140805-171523.zip5.06 KB